Conventionally, in a manufacturing process for a semiconductor device, a plasma etching process is performed via a resist mask to form a silicon oxide film or a glass based film (e.g., a BPSG film, a PSG film and the like) after a desired pattern. Further in such a plasma etching method, there is known a technique for performing micro-processing with a high accuracy by using a multi-layer resist mask.
Moreover, when plasma etching a glass based film, there is known a method in which a gaseous mixture of C4F6 gas, Ar gas, and O2 gas is used as a processing gas (see, for example, Japanese Patent Laid-open Application No. 2001-053061).
As described above, in the plasma etching process performed by using the multi-layer resist mask, in a case where holes are formed in a silicon oxide film and a glass based film formed under the silicon oxide film by using a gaseous mixture of C4F6 gas, Ar gas, and O2 gas, there is a problem that when an aspect ratio is increased, the frequency of occurrence of the so-called “mask collapse”, wherein the resist mask falls down during the etching process increases, thereby making it impossible to perform the desired plasma etching and eventually leading to a reduction of the yield.
The above-noted problem becomes conspicuously pronounced when the aspect ratio is greater than 10, a silicon nitride film is interposed between the silicon oxide film and the glass-based film, and the holes are of a longitudinal shape of a long diameter and a short diameter instead of a circular shape.
The above-described problem may be solved by replacing Ar gas with Xe gas in the gas mixture. Since, however, Xe gas is expensive, there is still a problem that manufacturing costs for the semiconductor devices are increased when using Xe gas.